Anti-spacer structure for improved gate activation

ABSTRACT

A method and structure for improving the gate activation of metal oxide semiconductor field effect transistor (MOSFET) structures are provided. The method of the present invention includes the steps of forming a structure having a plurality of patterned gate stacks atop a layer of gate dielectric material; forming a non-conformal film on the structure including the plurality of patterned gate stacks; blocking some of the plurality of patterned gate stacks with a first resist, while leaving other patterned gate stacks of said plurality unblocked; implanting first ions into the unblocked patterned gate stacks; removing the first resist and blocking the previously unblocked patterned gate stacks with a second resist; implanting second ions into the patterned gate stacks that are not blocked by the second resist; and removing the second resist and the non-conformal film. The inventive structure contains a non-conformal film formed on both horizontal and vertical surfaces of a structure including at least non-predoped patterned gate regions.

RELATED APPLICATIONS

[0001] This application-is related to attorney Docket No.FIS920010089US1 (14484) which is being concurrently filed with thisapplication.

FIELD OF THE INVENTION

[0002] The present invention relates to semiconductor devicemanufacturing, and more particularly to a method of fabricating a metaloxide semiconductor field effect transistor (MOSFET) in which the gateand source/drain regions are independently doped in a self-alignedmanner after the gate stack has been etched. The method of the presentinvention does not affect line width control, and no additionallithography steps are required.

BACKGROUND OF THE INVENTION

[0003] In today's most advanced semiconductor devices, the gate implantis also received by the source/drain regions. Typically, the maximumamount of dopant that the gate can receive is limited by the amount thatthe source/drain regions can tolerate. For example, currentstate-of-the-art NFETs use phosphorus for the source/drain regions. Iftoo much phosphorus is implanted into the source/drain regions, thenlateral phosphorus diffusion may be excessive causing degraded shortchannel effects. On the contrary, implanting high doses of phosphorus(on the order of about 5B15 cm⁻² or greater) into the gate reduces thegate depletion effect and improves the device characteristics.

[0004] In some prior art processes, wider source/drain spacers are usedto accommodate a higher dose of phosphorus into the source/drainregions. However, this causes the series resistance of the transistor tosignificantly increase.

[0005] If arsenic is used for the source/drain doping, achievingcomparable gate activation as phosphorus is difficult for the samethermal cycle. In order to achieve maximum flexibility in achieving theleast poly depletion and best short channel effect control, independentdoping of the source/drain regions and the gate regions is desirable.

[0006] It would thus be beneficial if a method would be developed thatwas capable of independent doping of the gate region and thesource/drain regions. Such a method would achieve improvements in thegate region of the device without negatively impacting the source/drainregions of the device.

[0007] One possible prior art approach for independent doping of thegate and the source/drain regions includes the use of a so-called gatepredoping scheme. A typical gate predoping scheme of the prior artincludes the steps of:

[0008] (i) depositing polysilicon onto a surface of a gate dielectricwhich is formed atop a semiconductor substrate;

[0009] (ii) using a first lithographic step to block the PFET region;

[0010] (iii) implanting ions into the NFET polysilicon material;

[0011] (iv) stripping the resist employed in step (ii);

[0012] (v) using a second lithographic step to block the NFET region;

[0013] (vi) implanting ions into the PFET polysilicon material;

[0014] (vii) stripping of the resist; and

[0015] (viii) etching the gate stack region.

[0016] In this prior art process, an activation annealing step istypically performed between steps (vii) and (viii) mentioned above.

[0017] A major disadvantage of this prior art integration scheme is thatthe implants are performed before the gate stack has been etched. Thisleads to poor line width control since the P-type polysilicon will etchdifferently than the N-type polysilicon. Also, if the implant conditionis changed, the gate etch steps needs to be re-optimized again since adifferent doping in the gate region will change the etchcharacteristics. Another major disadvantage of the aforementioned priorart gate predoping scheme is that it requires two additional lithographysteps, e.g., steps (ii) and (v) mentioned-above, prior to etching of thegate region. A yet further disadvantage of this prior art process isthat the different etching rates may result in recessing a portion ofthe substrate.

[0018] In view of the above drawbacks with prior art methods, there is acontinued need for providing a method which is capable of independentdoping of the gate and the source/drain regions that will allow foroptimizing the doping in the gate and source/drain regions independentlyso that improved device characteristics can be achieved without thecompromise between gate depletion and series resistance.

SUMMARY OF THE INVENTION

[0019] One object of the present invention is to provide a method offabricating a MOSFET device which is capable of independent doping ofthe gate and the source/drain regions.

[0020] A further object of the present invention is to provide a methodof fabricating a MOSFET device which has reduced gate depletion,improved device characteristics and limited lateral diffusion of dopantin the source/drain regions as well as the source/drain extensionregions.

[0021] Another object of the present invention is to provide a method offabricating a MOSFET device which has improved series resistance andline width control.

[0022] A yet further object of the present invention is to provide amethod of fabricating a MOSFET device in which gate predoping is avoidedand the number of lithographic steps is reduced.

[0023] These and other objects and advantages are achieved in thepresent invention by utilizing an anti-spacer structure. The anti-spacerstructure of the present invention enables independent doping of thegate and source/drain regions in a self-aligned manner after the gatestack etch so that line width control is not affected, and no additionallithography steps are required. The anti-spacer structure employs a thinfilm (or stack of films) having poor step coverage that is deposited onthe etched gate stack either before or after the source/drain regionsand/or extension implants are formed.

[0024] It is noted that the lack of step coverage of the inventiveanti-spacer structure enables the source/drain regions and thesource/drain extensions to be blocked during gate implanting, while thesidewalls of the gate are exposed and are thus able to be implanted atan angle. The film having a lack of step coverage is referred to hereinas a non-conformal film. The non-conformal film (or stack of films) maybe an organic or inorganic film which may be selectively removed afterthe gate is implanted. The non-conformal film is thick across horizontalsurfaces present in the structure, yet the non-conformal film is thinacross vertical surfaces present in the structure. In some embodiments,the non-conformal film is non-existent on the vertical surfaces, i.e.,vertical gate region. The variation of thickness in the non-conformalfilm permits the selective doping of the gate region, while blocking thesource/drain regions and source/drain extensions from the gate implant.

[0025] One aspect of the present invention thus relates to a method offabricating a MOSFET device which comprises the steps of:

[0026] (a) forming a structure having a plurality of patterned gatestacks atop a layer of gate dielectric material;

[0027] (b) forming a non-conformal film on said structure including atleast said plurality of patterned gate stacks;

[0028] (c) blocking some of the plurality of patterned gate stacks witha first resist, while leaving other patterned gate stacks of saidplurality unblocked;

[0029] (d) implanting first ions into said unblocked patterned gatestacks;

[0030] (e) removing said first resist and blocking said previouslyunblocked patterned gate stacks with a second resist;

[0031] (f) implanting second ions into said patterned gate stacks thatare not blocked by said second resist; and

[0032] (g) removing said second resist and said non-conformal film.

[0033] Note that source/drain regions and source/drain extensions may beformed prior to performing step (b) above, after step (d) and step (f),or after step (g). When the source/drain regions and source/drainextensions are formed prior to performing step (b), it is necessary toform sidewall spacers on the vertical sidewalls of each patterned gatestack region. These spacers are then removed before conducting steps(b)-(g) of the present invention. In a preferred embodiment of thepresent invention, the source/drain extensions are formed beforeformation of the source/drain regions.

[0034] In the present invention, the first ions employed in step (d) maybe the same or different from the second ions employed in step (f). In apreferred embodiment of the present invention, the first ions aredifferent from the second ions. Note that in some embodiments, the ionsused in steps (d) and (f) are the same, but different ion dosages areemployed in each step so as to form doped gate regions having differention concentrations.

[0035] In addition to providing a method of independent doping of thegate, source/drain regions and the source/drain extensions, the presentinvention also relates to a semiconductor structure, e.g., anti-spacerstructure, which includes the non-conformal film thereon. Specifically,the inventive structure of the present invention, which is anintermediate structure for the final MOSFET-containing device,comprises:

[0036] a semiconductor substrate having a layer of gate dielectricmaterial formed on a surface thereof;

[0037] a plurality of patterned gate regions formed on said layer ofgate dielectric material, said plurality of patterned gate regions notbeing pre-doped; and

[0038] a non-conformal film formed atop exposed surfaces of saidsubstrate or said layer of gate dielectric and said plurality ofpatterned gate regions, wherein said non-conformal film is thicker overhorizontal surfaces, while being thinner over vertical sidewalls of eachof said patterned gate regions.

[0039] Note that in some embodiments of the present invention, thepatterned gate regions include a reoxidation material formed thereon.

Brief Description of the Drawings

[0040] FIGS. 1-7 are pictorial representations (through cross-sectionalviews) showing the basic processing steps of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0041] The present invention, which provides a method of fabricating aMOSFET device in which independent doping of the gate, source/drainregions and source/drain extensions is achieved, will now be describedin greater detail by referring to the drawings that accompany thepresent application. It is noted that in the accompanying drawings likeand/or corresponding elements are referred to by like referencenumerals.

[0042] Reference is first made to FIG. 1 which illustrates an initialstructure that is employed in the present invention. Specifically, theinitial structure shown in FIG. 1 comprises semiconductor substrate 10,a layer of gate dielectric 12 formed on a surface of semiconductorsubstrate 10, and a plurality of patterned gate stacks 14 formed onportions of gate dielectric 12.

[0043] The structure shown in FIG. I is comprised of conventionalmaterials well know in the art and it is fabricated utilizing processingsteps that are also well known in the art. For example, semiconductorsubstrate 10 comprises any semiconducting material including, but notlimited to: Si, Ge, SiGe, GaAs, InAs, InP and all other III/Vsemiconductor compounds. Semiconductor substrate 10 may also include alayered substrate comprising the same or different semiconductingmaterial, e.g., Si/Si or Si/SiGe, as well as a silicon-on-insulator(SOI) substrate. The substrate may be of the n- or p-type depending onthe desired device to be fabricated.

[0044] Additionally, semiconductor substrate 10 may contain activedevice regions, wiring regions, isolation regions or other like regionsthat are typically present in MOSFET-containing devices. For clarity,these regions are not shown in the drawings, but are nevertheless meantto be included within region 10. In one highly preferred embodiment ofthe present invention, semiconductor substrate 10 is comprised of Si.

[0045] Next, a layer of gate dielectric material such as an oxide,nitride, oxynitride or any combination and multilayer thereof, is thenformed on a surface of semiconductor substrate 10 utilizing aconventional process well known in the art. For example, the layer ofgate dielectric material may be formed by utilizing a conventionaldeposition process such as chemical vapor deposition (CVD),plasma-assisted CVD, evaporation or chemical solution deposition, oralternatively, the gate dielectric material may be formed by a thermalgrowing process such as oxidation, nitridation or oxynitridation

[0046] The thickness of the layer of gate dielectric material formed atthis point of the present invention is not critical to the presentinvention, but typically, gate dielectric 12 has a thickness of fromabout 1 to about 20 nm after deposition, with a thickness of from about1.5 to about 10 nm being more highly preferred. It is noted that thegate dielectric material employed in the present invention may be aconventional dielectric material such as SiO₂ or Si₃N₄, oralternatively, high-k dielectrics such as oxides of Ta, Zr, Hf, Al orcombinations thereof may be employed. In one highly preferred embodimentof the present invention, gate dielectric 12 is comprised of an oxidesuch as SiO₂, ZrO₂, Ta₂O₅, HfO₂ or Al₂ 0 ₃.

[0047] After forming gate dielectric 12 on a surface of semiconductorsubstrate 10, a plurality of patterned gate regions 14 are formed atopthe layer of gate dielectric. The patterned gate regions are formedutilizing a conventional process which includes the steps of: depositingat least a gate material, and patterning said gate material vialithography and etching. The lithography step includes applying aphotoresist to the gate material, exposing the photoresist to a patternof radiation and developing the pattern utilizing a conventionaldeveloper solution. Etching is performed utilizing a conventional dryetching process such as reactive-ion etching, plasma etching, ion beametching or laser ablation. Following the etching process, thephotoresist is removed from the structure utilizing a conventionalstripping process well known in the art so as to provide the structureshown, for example, in FIG. 1.

[0048] In one embodiment of the present invention, the gate dielectricis patterned at this point of the inventive process and thenon-conformal film is subsequently formed on exposed surfaces of thesubstrate as well as vertical sidewalls of the patterned gate stackregion, including the patterned gate dielectric.

[0049] It is noted that each of patterned gate regions 14 shown in FIG.1 includes at least a gate material which may further contain anoptional dielectric capping layer formed thereon. The term “gatematerial” as used herein denotes a conductive material, a material thatcan be made conductive via a subsequent process such as ionimplantation, or any combination thereof. Illustrative examples ofsuitable gate materials that can be employed in the present inventioninclude, but are not limited to: polysilicon, amorphous silicon,elemental metals such as W, Pt, Pd, Ru, Rh and Ir, alloys of theseelemental metals, suicides or nitrides of these elemental metals, andcombinations thereof, e.g., a gate stack including a layer ofpolysilicon and a layer of conductive metal. A highly preferred gatematerial employed in the present invention is a gate material that iscomprised of polysilicon or amorphous silicon.

[0050] The gate material is formed on the surface of gate dielectric 12utilizing conventional deposition processes well known in the artincluding, but not limited to: CVD, plasma-assisted CVD, evaporation,plating, or chemical solution deposition. When metal suicides areemployed, a conventional silicide process may be used in forming thesilicide layer. One such silicide process that can be used in thepresent invention includes the steps of: first forming an elementalmetal, annealing the elemental metal so as to form a metal silicidelayer therefrom, and removing any unreacted elemental metal utilizing aconventional wet etch process that has a high selectivity for removingunreacted metal as compared to silicide.

[0051] It is noted that in embodiments wherein a gate stack is employed,e.g., a stack of polysilicon and elemental metal, an optional diffusionbarrier (not shown in the drawings) may be formed between each layer ofthe gate stack. The optional diffusion barrier, which is formedutilizing conventional deposition processes such as those mentionedhereinabove, is comprised of a material such as SiN, TaN, TaSiN, WN, TiNand other like materials which can prevent diffusion of a conductivematerial therethrough.

[0052] As stated above, an optional dielectric capping layer may bepresent atop the gate material. When present, the optional dielectriccapping layer is comprised of an oxide, nitride or oxynitride and it isformed utilizing a conventional deposition process such as, for example,CVD or plasma-assisted CVD. Alternatively, a conventional thermalgrowing process such as, for example, oxidation, may be used in formingthe optional dielectric capping layer.

[0053] In one embodiment of the present invention, source/draindiffusion regions 11 and source/drain extensions (note that thesource/drain extensions are not shown separately in the drawings;instead they are meant to be included within region 11) may be formed inthe semiconductor substrate at this point of the present invention.Typically, the source/drain extensions are formed prior to the deepsource/drain regions utilizing conventional ion implantation andannealing processes well known in the art. In the embodiment shown,disposable sidewall spacers (not shown) would be formed on the verticalsidewalls of each patterned gate region utilizing deposition and etchingprocesses well known in the art. After formation of the source/drainextension regions and source/drain diffusion regions, the disposablespacers are removed utilizing a conventional etching process well knownto those skilled in the art.

[0054] In other embodiments, the source/drain diffusion regions andsource/drain extension regions may be formed after implanting into eachgate region or following implantation into both gate regions. A gateactivation anneal, as mentioned hereinbelow, may follow the implantationinto the gate region. Note that in FIG. 1 the source/drain diffusionregions and source/drain extensions are shown therein.

[0055] In yet another embodiment of the present invention, the patternedgate stack is subjected to a conventional reoxidation process prior toforming the non-conformal film on the structure.

[0056] After providing the structure shown in FIG. 1, non-conformal film16 is formed across the entire surface of the structure including atopgate dielectric 12 and patterned gate regions 14 (note both thehorizontal and vertical sidewalls of the patterned gate regions containthe non-conformal film). The resultant structure including non-conformalfilm 16 is shown, for example, in FIG. 2. It is noted that the term“non-conformal film” is used in the present invention to denote a filmthat is thicker on the horizontal surfaces of the gate material and thegate dielectric, and thinner on the vertical surfaces of the gatematerial, or optionally the material formed by reoxidation. In someembodiments, the non-conformal film may be non-existent on the verticalsurfaces of the gate material. In the embodiment wherein the gatedielectric is patterned, non-conformal film 16 is formed on exposedsurfaces of the substrate as well as the patterned regions (includingpatterned gate dielectric and patterned gate stack). As statedpreviously, the variation in thickness of the non-conformal film allowsfor blocking of the source/drain diffusion regions during the doping ofthe gate material through the sidewalls thereof.

[0057] The non-conformal film is formed in the present inventionutilizing any deposition process that is capable of forming such a layeror multilayer thereof on a structure. Following the deposition of thenon-conformal film, an isotropic etching process such as a dry or wetetch process that is capable of uniformly removing the non-conformalfilm, yet is selective to the gate material, substrate, and optionalliner (to be discussed hereinbelow) may be used to thin the film by thesame amount on both the vertical and horizontal surfaces. This processof deposition and etching may be repeated any number of times, asrequired. Alternatively, the non-conformal film may be formed utilizinga conformal deposition process and thereafter a lateral etching processmay be used in forming the non-conformal film on the structure.

[0058] Non-conformal film 16 employed in the present invention may becomprised of a dielectric material, such as an oxide, nitride oroxynitride, which is different from the gate dielectric. Differentdielectric materials are required in the present invention so as toprovide the necessary etch selectivity needed for removing thenon-conformal layer in a subsequent etching step. Alternatively, thenon-conformal film may be comprised of a photoresist material or anotherorganic, or inorganic film which may be selectively removed followingthe gate implanting steps.

[0059] In one embodiment of the present invention, an optional linerthat is thin and conformal may be formed on the structure prior toformation of the non-conformal film. The optional liner (not shown inthe drawings) is comprised of an insulating material such as Si₃N₄ orSiO₂. Note that optional liner assists in the subsequent removal of thenon-conformal film.

[0060]FIG. 3 shows the structure that is obtained after some ofpatterned gate stacks 14 are blocked with first resist 18, while leavingother patterned gate stacks unblocked. Specifically, the structure shownin FIG. 3 is formed utilizing conventional lithography which includesthe steps of: applying a layer of first resist 18, exposing the layer offirst resist to a pattern of radiation and developing the patternutilizing a conventional resist developer.

[0061] With first resist 18 in place, the unblocked patterned gatestacks are then subjected to an ion implantation step which is capableof implanting ions into the exposed gate regions that are not blockedwith first resist 18. In accordance with the present invention, this ionimplantation step includes the use of an angled ion implant wherein anion of a first conductivity type (N or P) or neutral is implanted intothe gate material. The ion dose used in this implant step of the presentinvention may vary, but typically an ion dose of about 5E15 cm⁻² orgreater is employed. This step of the present invention, i.e., the firstangled ion implantation step, is shown in FIG. 4. Note that in thedrawing reference numeral 20 is used to denote the first ions (firstconductivity type or neutral) that are being implanted within the gatematerial.

[0062] It is noted that the ions implanted at this step of the presentinvention are not implanted into the substrate due to the presence ofthe thicker horizontal portions of non-conformal film 16. Instead, theions are implanted into the gate region through the thinner verticalportion of the non-conformal film 16.

[0063] In an optional embodiment of the present invention, the gatematerial is preamorphized prior to implanting the first ions into thegate material. When preamorphization occurs an ion such as Ge or Si isimplanted into the gate material. The preamorphization step is employedin the present invention to prevent channeling of the first ions intothe channel region of the device.

[0064] In some embodiments of the present invention, the unblockednon-conformal film shown in FIG. 4 may be removed at this point of theinventive method and source/drain extensions and source/drain diffusionregions 11 may be formed into the surface of substrate 10 as describedhereinabove. This embodiment is not shown in the drawings since thesource/drain extensions and source/drain diffusion regions have beenpreviously formed into the surface of substrate 10. Note that when suchan embodiment is performed, no additional lithographic masking layersare necessary.

[0065] After the unblocked portions of the patterned gate regions havebeen subjected to ion implantation, first resist 18 is removed from thestructure utilizing a conventional stripping process well known in theart and patterned second resist 22 is formed atop the previously ionimplanted gate regions providing the structure shown in FIG. 5. Thepatterned second resist is formed utilizing conventional lithography.

[0066]FIG. 6 shows the structure during a second angled ion implant stepwherein second ions (second conductivity type (N or P) or neutral) thatare the same or different from the first ions are implanted into thegate region. In a preferred embodiment, different conductivity ions areemployed. Note that reference numeral 24 denotes the second ions thatare implanted into the gate region at this point of the presentinvention. The ion dose used in this implant step may vary, buttypically an ion dose of about 5E15 cm⁻² or greater is employed. Apreamorphization as mentioned herein above may be employed prior to thisimplantation step.

[0067] In some embodiments of the present invention, the unblockednon-conformal film shown in FIG. 6 may be removed and source/drainextensions and source/drain diffusion regions 11 may be formed into thesurface of substrate 10 as described hereinabove. This embodiment is notshown in the drawings since those regions have been previously formedinto the surface of substrate 10.

[0068] Next, and as shown in FIG. 7, second resist 22 is removedutilizing a conventional stripping process well known in the art andthereafter, and if not previously done, non-conformal film 16 is removedfrom the entire structure utilizing a conventional etching process thatis highly selective in removing the non-conformal film.

[0069] It should be noted that after each of the above-mentioned angledimplants, the gate regions may be activated utilizing a conventionalactivation annealing process that is well known to those skilled in theart. Note that the gate regions may be annealed separately afterimplanting each gate region, or the gate regions may be annealed at thesame time. Typical annealing conditions that may be used in the presentinvention for activating the gate regions include an annealingtemperature of about 900° C. or greater and an annealing time of about15 seconds or less. Other annealing times and annealing temperatures canalso be employed. The activation annealing step is typically carried outin N₂, an inert gas such as He or Ar, or mixtures thereof.

[0070] In some embodiments of the present invention, the activation ofthe gate regions occurs in a single step prior to completely removingnon-conformal film 16 from the structure. In another embodiment of thepresent invention, the activating of the gate regions may be performedafter removing the non-conformal film from the structure. In such anembodiment, the source/drain diffusion regions and extension implantsmay be formed after the complete removal of the non-conformal film, butprior to activating the gate regions.

[0071] While the present invention has been particularly shown anddescribed with respect to preferred embodiments thereof, it will beunderstood by those skilled in the art that the foregoing and otherchanges in forms and details may be made without departing from thespirit and scope of the present invention. It is therefore intended thatthe present invention not be limited to the exact forms and detailsdescribed and illustrated, but fall within the scope of the appendedclaims.

Having thus described our invention in detail, what we claim as new anddesire to secure by the Letters Patent is:
 1. A method of fabricating ametal oxide semiconductor field effect transistor (MOSFET) devicecomprising the steps of: (a) forming a structure having a plurality ofpatterned gate stacks atop a layer of gate dielectric material; (b)forming a non-conformal film on said structure including at least saidplurality of patterned gate stacks; (c) blocking some of the pluralityof patterned gate stacks with a first resist, while leaving otherpatterned gate stacks of said plurality unblocked; (d) implanting firstions into said unblocked patterned gate stacks; (e) removing said firstresist and blocking said previously unblocked patterned gate stacks witha second resist; (f) implanting second ions into said patterned gatestacks that are not blocked by said second resist; and (g) removing saidsecond resist and said non-conformal film.
 2. The method of claim 1wherein step (a) comprising the steps of: forming at least one gatematerial on said gate dielectric and patterning said gate material vialithography and etching.
 3. The method of claim 2 wherein said at leastone gate material comprises a conductive material or a material that canbe made conductive.
 4. The method of claim 2 wherein said at least onegate material is selected from the group consisting of polysilicon,amorphous silicon, an elemental metal or alloys thereof, a silicide ornitride of an elemental metal and any combination thereof.
 5. The methodof claim 4 wherein said elemental metal is W, Pt, Pd, Ru, Rh or Ir. 6.The method of claim 2 wherein said at least one gate material iscomprised of polysilicon or amorphous silicon.
 7. The method of claim 1wherein said non-conformal film is formed by a non-conformal depositionprocess, a non-conformal deposition process and isotropic etching, or aconformal deposition process and lateral etching.
 8. The method of claim1 wherein said non-conformal film is thicker over horizontal surfaces ascompared with vertical surfaces.
 9. The method of claim 1 wherein saidnon-conformal film is comprised of an organic film, an oxide, a nitrideor an oxynitride.
 10. The method of claim 1 wherein said first resist isformed via lithography.
 11. The method of claim 1 wherein said firstions are comprised of a N-type dopant.
 12. The method of claim I whereinstep (d) is performed utilizing an angled ion implantation process. 13.The method of claim l wherein step (d) is performed utilizing an iondose of about 5E15 cm⁻² or greater.
 14. The method of claim 1 whereinsaid second resist is formed via lithography.
 15. The method of claim 1wherein said second ions are comprised of a P-type dopant.
 16. Themethod of claim 1 wherein step (f) is performed utilizing an angled ionimplantation process.
 17. The method of claim I wherein step (f) isperformed utilizing an ion dose of about 5E15 cm⁻² or greater.
 18. Themethod of claim 1 wherein source/drain extension regions andsource/drain diffusion regions are formed in a surface of asemiconductor substrate which is present beneath said gate dielectricprior to performing step (b).
 19. The method of claim 1 whereinsource/drain extension regions and source/drain diffusion regions areformed in a surface of a semiconductor substrate which is presentbeneath said gate dielectric following implant steps (d) and (f). 20.The method of claim 1 wherein source/drain extension regions andsource/drain diffusion regions are formed in a surface of asemiconductor substrate that is present beneath said gate dielectricafter performing step (g).
 21. The method of claim I wherein saidimplanted patterned gate stacks are activated after steps (d) or (e)using separate activation annealing steps.
 22. The method of claim 1wherein said implanted patterned gate stacks are activated using asingle activation annealing step after said removal of said secondresist or after said removal of said non-conformal film.
 23. Ananti-spacer structure comprising: a semiconductor substrate having alayer of gate dielectric material formed on a surface thereof; aplurality of patterned gate regions formed on said layer of gatedielectric material, said plurality of patterned gate regions not beingpre-doped; and a non-conformal film formed atop said layer of gatedielectric and said plurality of patterned gate regions, wherein saidnon-conformal film is thicker over horizontal surfaces, while beingthinner or non-existent over vertical sidewalls of each of saidpatterned gate regions.
 24. The anti-spacer structure of claim 23wherein said semiconductor substrate is comprised of a semiconductingmaterial selected from the group consisting of Si, Ge, SiGe, GaAs, InAs,InP, Si/Si, Si/SiGe and silicon-on-insulators.
 25. The anti-spacerstructure of claim 23 wherein said gate dielectric is comprised of anoxide, a nitride, an oxynitride or any combinations and multilayersthereof.
 26. The anti-spacer structure of claim 25 wherein said gatedielectric is comprised of an oxide selected from the group consistingof SiO₂, ZrO₂, Ta₂O₅, HfO₂ and A1 ₂O₃.
 27. The anti-spacer structure ofclaim 23 wherein said patterned gate stack region comprises at least onegate material.
 28. The anti-spacer structure of claim 27 wherein said atleast one gate material comprises a conductive material or a materialthat can be made conductive.
 29. The anti-spacer structure of claim 27wherein said at least one gate material is selected from the groupconsisting of polysilicon, amorphous silicon, an elemental metal oralloy thereof, a silicide or nitride of an elemental metal and anycombination thereof.
 30. The anti-spacer structure of claim 29 whereinsaid elemental metal is W, Pt, Pd, Ru, Rh or Ir.
 31. The anti-spacerstructure of claim 27 wherein said at least one gate material iscomprised of polysilicon or amorphous silicon.
 32. The anti-spacerstructure of claim 23 wherein said non-conformal film is comprised of anorganic film, an oxide, a nitride or an oxynitride.
 33. The anti-spacerstructure of claim 23 wherein said layer of gate dielectric is patternedand said plurality of patterned gate regions are formed on saidpatterned gate dielectric and said non-conformal film is formed onexposed surfaces of said substrate as well as patterned regions formedthereon.